While the engineering world is investing billions of dollars and thousands of hours into vehicle autonomy, there is still a long way to go.
Today’s best commercial offerings come in at a Level 2 (L2) out of 5 on the SAE Levels of Driving Automation scale. All in all, to get to Level 5 (L5), there will need to be improvements in both hardware and software.
The SAE Levels of Driving Automation. Image used courtesy of Autopilot Review
One startup working on developing the hardware intellectual property (IP) to advance the state of vehicle autonomy is VSORA.
Last week VSORA made headlines when it announced its new family of petaFLOPS-capable companion processors.
This article will look at the need for advanced hardware for achieving Level 5 autonomy and dive deeper into VSORA’s newest chipset family.
The Need for Advanced Hardware
According to some, one of the biggest roadblocks to achieving Level 5 autonomy is the underperformance of our current hardware. Basically, there are multiple aspects of autonomous vehicles that require exceptionally high compute power.
First, all autonomous vehicles work with a lot of data. Today it is common for these vehicles to use as many as 40 sensors on-system (e.g., camera, LIDAR), many of which produce extremely high throughput.
To effectively use all of this data, vehicles require incredibly high compute power.
The execution flow of data in a self-driving vehicle. Image used courtesy of Abalta
This challenge is even further exacerbated by the real-time requirements of autonomous vehicles. These vehicles require decision-making in real-time, meaning that in a matter of milliseconds, data must be collected, fused, and processed, and then decisions need to be made and executed.
To achieve this amongst the enormous amount of data requires very powerful compute.
Hoping to propel and ease this compute challenge is VSORA’s latest chipset.
VSORA’s Tyr Chipset
Last week, startup VSORA released a new family of chips that claim to help support autonomy up to L5.
The Tyr family of chips are companion processors aiming to offload the heavy AI and signal processing tasks from the system’s main processor.
An overview of the AD1028 architecture used in the Tyr family. Image used courtesy of VSORA
This architecture combines an advanced digital signal processing (DSP) unit for complex signal processing, an AI unit consisting of a series of identical cores, and a tightly coupled memory.
The flagship offering of this family is the Tyr3, a chip consisting of 256k MACs in the AI core and 2,048 ALUs for DSP applications.
The Tyr3 is said to achieve 1,032 TFLOPS (1.032 PFLOPS) of compute, while the family as a whole is capable of achieving as little as 10 Watts.
According to VSORA, this new family of chips could significantly simplify the leap from L2 to L5 by offering a high-performance, easily integrated solution for existing hardware infrastructure.
The Push Towards Level 5 Autonomy
While some people, like VSORA, claim that our current hardware is not yet ready to achieve Level 5, others disagree.
It is worth noting that Elon Musk is quoted saying that he believes that the hardware inside of a Tesla can support Level 5 autonomy: for them, the real roadblock appears to be software.
Regardless of who is correct, there is no doubt that improvements in hardware will only be a good thing. VSORA seems to have done exactly this with its new Tyr family of companion processors.
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