NXP’s MCX MCUs Shoot for an Accessible Edge AI Design

NXP’s MCX MCUs Shoot for an Accessible Edge AI Design



The term edge computing often gets thrown around a lot by engineers and marketers alike, but it can sometimes mean many different things to many different people. Various applications may require additional optimizations out of their hardware, be it wireless connectivity, ultra-low power, or blending power and performance. The result is that edge computing platforms can look very different architecturally from one another.

This diversity creates challenges for designers, such as: 

  • Barriers to entry
  • Difficulty scaling
  • Inability for software reusability

Today, NXP has addressed these challenges head-on with the release of the MCX portfolio, a new family consisting of 4 MCUs, each targeting a different need within edge computing.

 

A timeline of MCU evolution to the latest MCX. Image used courtesy of NXP

 

Recently, All About Circuits had the chance to speak with CK Phua, Product Manager of Microcontrollers at NXP, and Ali Osman Ors, Director of AI ML Strategy and Technologies at NXP, to hear more about the new MCUs firsthand.

 

MCX N—Mixing NPU and ML

Out of the four new MCUs released by NXP, the flagship of the offering is the MCX N Advanced series of MCUs.

Built around an Arm Cortex M33 core, NXP claims that the MCX N is explicitly designed to offer high performance and efficiency for real-time inference applications on edge. To do this, the MCX introduces NXP’s in-house neural processing unit (NPU) architecture into the mix. 

As Osman explains, “…the MCX N integrates a machine learning (ML) accelerator, NPU which is an NXP inhouse designed architecture. We’ve created the design to be quite scalable, ranging from 32 operations per cycle all the way beyond 2000 operations per cycle with clock speed being a multiplier.”

 

Block diagram of the NXP NPU accelerator.

Block diagram of the NXP NPU accelerator. Image used courtesy of NXP

 

Targeting TinyML applications, the MCX N offers 1 MB of memory while providing support for INT16 but is optimized for performance with INT8

Osman continues, explaining: 

 

“That’s really the key piece. This is coming in from a push to enable more TinyML capability on a traditional MCU device. For this, we optimized performance for a quantized INT8 model. Anything floating point would fall back to the Cortex M33.”

 

Beyond the NPU, the MCX N targets performance by offering clock speeds from 150 to 250 MHz and a broad range of peripherals such as an integrated DSP (digital signal processor) and EdgeLock secure subsystem. Altogether, NXP claims that the MCX N Advanced offers best-in-class performance and power efficiency.

 

MCX L Targets Ultra-low Power

Following the high-performance ML offering, NXP also introduces the MCX L ultra-lower power MCU. 

Designed for power-critical applications such as battery-powered devices, the MCX L is meant to minimize power consumption as much as possible. From a hardware perspective, it is built around a 50-100 MHz Arm Cortex-M33 core and targets power consumption through architectural means.

According to NXP, beyond voltage and frequency scaling, the MCX L aims to minimize subthreshold leakages to achieve a low power consumption offering. 

Phua clarifies, “The current trend for lower power is always the voltage and frequency scaling. The L series will go beyond that. We instead focus on sub-threshold and other techniques that are going to be applied to achieve this low active power looks like this.” 

These other techniques include body biasing, active switching, and judicious power management to the I/O power.

 

MXC A and W: The Essential and Wireless

The final two offerings from the MCX family come from the MCX A Essential and MCX W Wireless offerings.

Designed to be an easy-to-use, entry-level offering, the MCX A shares the same Arm Cortex-M33 core as the rest of the family but with much functionality toned down. The MCX A offers a single-pin power supply and a low pin count for cost-constrained applications. 

 

“The A is the same baseline with zero peripherals. As the users start using and outgrow the functions or the memory needed at the entry-level, they can move up. And when that happens, we will attempt to give the drop in as compatibility over there.”

 

An overview of the MCX portfolio.

An overview of the MCX portfolio. Image used courtesy of NXP

 

Finally, the MCX W is NXP’s wireless MCU offering. Featuring a 32 to 150 MHz Arm Cortex M33 core, an efficient Bluetooth LE radio, and a high level of on-chip integration, the MCX W aims to offer low-power narrowband connectivity and simplify adding wireless connectivity to IoT devices.

 

Easing Design for the Edge

With the new family of MCUs, NXP hopes to make it as easy as possible to migrate a design from one use case to another. 

By each member sharing the same architecture, featuring a Cortex-M33 core, the MCX family strives to ease edge design by creating an interoperable portfolio, making switching from use-case to use-case significantly easier for the engineer.

 

Featured image used courtesy of NXP



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